资源列表
multiply
- 四位加法器的VHDL代码，实现四位加法器FPGA实现。-Four adder VHDL code to achieve the four adder FPGA.
CRC-8
- VHDL code for CRC-8 computing using 32 bit input (parallel)
uart
- PC机上开串口调试助手，发送一个字符到开发板（中间通过串口线相连） FPGA收到字符后，回发给PC机上，在串口助手上显示 -Open the PC serial debugging assistant, to send a character to the development board (middle connected by a serial line) After the FPGA received character is sent back to the PC, is
EDA
- 设信号ＣＨ表示计算路程脉冲，每０.１公里变化一个周期．出租车三公里内为起步价７.０元，超过三公里，每公里２.４元．设置一个开车键，停止状态按动一次表示开车，开车状态按动一次表示下车．一个暂停键，暂停是停止收费，再次按动继续收费．七段码显示当前价格和路程．且所有七段码为动态显示． 如果有谁会的话，帮帮忙吧，写些主要的程序就行了-Established that the calculation of CH distance signal pulse, 0.1 kilometers of each
IMG
- 这是一个VHDL编写的VGA驱动程序 能显示彩条-This is a VHDL prepared VGA driver can display color
VHDL
- 序列检测器设计VHDL源程序 任意输入串行数据串-VHDL source code sequence detector design arbitrary string of serial data input
ALU
- alu设计，实现简单的ALU功能，教学专用-alu design, implementation, simple ALU functions, special education
square_root
- 平方根运算的hdl语言实现，包含测试激励，已验证通过。-The square root hdl language, including the test stimuli, has been verified.
test
- dac900驱动，使其产生正弦波，其中关于ram的查询以及pll倍频模块，该代码只是总的调用-DAC900 driver to produce a sine wave, which RAM query and PLL multiplier module, the code is just the total number of calls
fifo64x8_tb
- Testbench for Xilinx 64x8 FIFO.
ex1.v
- 用Verilog HDL 实现的4位二进制全加器。-4-bit full adder implemented with Verilog HDL
clktest
- 在开发过程中，通常要进行时钟可靠性测试，主要有相位的变化 、占空比的变化。本代码实现了时钟相位变化和占空比的变化。-In the development process, usually the reliability of the test clock, there are phase changes, the duty cycle changes. Implementation of the code phase of the clock change and the duty cycle