资源列表
Program
- 用VHDL状态机设计一个8位序列信号检测器。-Design a state machine in VHDL 8-bit serial signal detector.
edmxk1b
- 产生脉宽和脉停，根据不同档位可以选择不同的脉宽和脉停。占用资源少。已经实际使用-To generate pulse width and pulse stopped, according to the different stalls can choose a different pulse width and pulse stop. Occupy less resources. Have been the actual use of
js
- 绞车传感器的计数程序代码 计算四倍频的程序 -Winch sensor count code to calculate the fourth harmonic of the program
counters
- 用VHDL编写的最大值为255的计数器，供初学者参考-A 255 counter of VHDL，for Beginners Reference
servo
- Verilog编写的辉盛9g舵机控制程序，clk：25MHz，输入角度（0~180），输出PWM，直接连到舵机引脚上即可使用-Verilog prepared Fraser 9g servo control procedures, clk: 25MHz, input angle (0 to 180), the output PWM, directly connected to the steering pin can be used
MFSK.vhd
- 多进制数字频率合成系统VHDL程序,包含2进制、16进制。-Multi-band digital frequency modulation (MFSK) system VHDL program
conta_60
- vhdl count 60, kinda simple but i used it for a clock
jyfp
- 将输入1kHZ的信号分频为50HZ的分频-1kHZ the input signal frequency is 50HZ crossover device
Decoder-3x8
- Decoder 3x8 Verilog code... This is for Xilinx Spartan 3E board
waterline_adder.rar
- 这是一个用Verilog编写的四级流水线加法器,This is a Verilog prepared with four pipeline adder
sqrt
- 实现任意位数的开方算法，但是不是浮点的算法，-Square root algorithm for arbitrary digit, but not floating-point algorithm, thanks
HDB3-Decoding
- hdb3解码程序，输入时01代表+1,10代表-1,程序经仿真通过。-hdb3 decoder, input 01 representative of the representative+1,10-1, the program adopted by the simulation.