资源列表
beep
- 用verilog实现的蜂鸣器报警，实现摩斯码报警。-Using Verilog to achieve the buzzer alarm, the realization of Moss code alarm.
bi_bus
- 基于FPGA的双向端口的开发，该方法简单易懂，便于读者理解和应用-FPGA-based bi-directional port development, the method is simple and easy to understand, easy to readers to understand and apply
serial2parallel256
- Complex Add in Vhdl with generic parameter
phaseconrol
- 将10Khz的输入信号经过分频得到两路互补的方波信号，方波信号的频率由分频计数初值决定。然后将分频后的方波进行移相，从而得到另外两路方波信号，移相的大小也由计数器的的初值决定。-After the 10Khz frequency input signals are two complementary square wave signals, square wave signal frequency by a frequency count of initial decision. And the
ADC_TCL5510-verilog
- verilog 驱动TLC5510代码，TLC5510是高速的AD，可达20MHz-verilog code driven TLC5510, TLC5510 is a high-speed AD, up to 20MHz
FIBONACCI_SERIES
- fibonacci series in vhdl
WROM
- Twiddle factors in ROM
clk-10divide
- 基于verilog编写的十分频时钟，简单易懂，欢迎大家下载和学习-Based on the frequency counter verilog prepared very easy to understand, are welcome to download and learn
adder32bit
- vhdl code for 32 bit binary addition
22
- 使用VHDL实现16进制的计数器的算法程序-Use VHDL to achieve 16 of the counter-band algorithm procedure
SRDFF
- Zip file contains the shiftregister code using verilog HDL
key-dejitter
- 按键去抖模块，避免按键抖动引起的系统误操作。FPGA时钟频率25.000MHZ-Key de-jittering module to avoid system misoperation caused by key-jitter. FPGA clock frequency 25.000MHZ