资源列表
DE2_70_LTM
- VERILOG语言环境的LTM显示开发封装模块。-VERILOG language environment of the LTM display development encapsulated module.
texi
- 出租车计费系统的源码，包括仿真结果，用quartusii调通。
VHDL_Complex_Examples
- Some slides with complex vhdl examples. There you can find UART,ROMs,RAMs and other source codes and details for every one
zhengxuanxinhaofashengqi
- 使用ISE 软件调用IP 核进行数字集成电路设计的方法，正弦信号发生器-Use ISE software call IP core digital IC design method, sine signal generator
beta1_1
- 自已写的幅频转换vhdl代码，ad用的是tl549DA用的是5620。1602显示-To write their own amplitude-frequency converter vhdl code, ad using a tl549DA using a 5620.1602 Show
summer camp xdc
- Design constraints define the requirements that must be met by the compilation flow in order for the design to be functional on the board • Over-constraining and under-constraining is bad, so use reasonable constraints that correspond to your requ
selectionadevelopment-of-Altera_FPGA
- Altera_FPGA的选型及开发 讲解了Altera_FPGA的选型开发与设计应用-The selection and development of Altera_FPGA To Selection developers to explain Altera_FPGA the design applications
xapp1052
- 赛灵思官方pcie例程，官网下载需要注册登录，这边给大家另一个选择(Xilinx PCIe official routines, the official website to download the required registration login, here give you another choice)
calc
- 用FPGA设计的简易计算器,包括按键模块,数码管模块-Use the FPGA design simple calculator, including key module, digital tube module
cpu-design
- VHDL设计的一个可综合的精简指令集的CPU，加上外围模块，类似与51单片机，当然还缺少很多功能，只是雏形，供大家交流-VHDL design of an integrated RISC CPU, coupled with external modules, exhausted and 51 single-chip, of course, the lack of many features, but prototype for all to share
Exp10_One_Wire
- 基于FPGA和Nios II设计的1-wire数字温度计-failed to translate
random_num_gen
- Combination is formed by permuting and XORing 32 bits of LFSR and CASR