资源列表
testmult_top
- TESTBENCH测试程序，小数加法器的实现，小数位设为2位，将其小数位与整数位分别显示出来。-TESTBENCH test procedures, the implementation of decimal adder, is set to two decimal places, its decimal places, respectively, with the integer-bit display.
FIR
- 10阶的F.I.R滤波器设计的 verilog代码-Verilog code for the 10-order FIR filter design
div
- 两个3位二进制数的除法，结果（整数商）输出到数码管显示-verilog multply
ram
- vhdl code for simple ram block
crc16
- crc16 module for SDIO DAT line calculation
IIR_Filter
- 一个简要的低通滤波程序IIR Filter QuartusII7-IIR Filter QuartusII7
counter
- vhdl code for counter
clk_generator
- 时钟分频代码，PWM产生 RTL 源代码。-clock divider，PWM generator RTL Source Code
d_ff_cout_tb
- D FLIP FLOP TEST BENCH
CRC
- CRC 编码-CRC code. . . . . . . . . . . . . . . . .
dial
- 读入拨码开关8位0 1状态在8位7段数码管相应位上显示0或1。-Reads DIP switch 8 0 1 state in the 8-bit 7-segment display the corresponding bit 0 or 1.
2stageMillerC2012v6
- 带米勒补偿效应的二级运算放大器实现电路图，在Hspice中实现的代码-Two operational amplifiers with Miller compensation effect achieved schematics, code implemented in Hspice