资源列表
ADC_16bit
- 16位ADCverilog hdl 代码
bianma
- 用VHDL语言实现8-3线编码器，16-4线编码器
uart
- 串口发送和接收，异步串口中的发送和接收模块，功能较为简单。-Serial transmission, asynchronous serial port of the sending module, function is relatively simple.
gcd2
- GCD算法的FSM+D实现。即利用有限状态机和数据路径分开-GCD algorithm of the FSM + D realize it is using finite state machine and data path separate
despread
- De-pread s the received voice signal.
S3E_AnalogIO
- it is a analog i/o interface written in verilog .it will work on spartan 3 xilini devices.
barrel_shift
- This project si barrel shifter for an 8-bit
CCMU
- 代码是一个复数乘法器，两个复数相乘，只用到了2个实数相乘，运算量少-Code is a complex multiplier, two complex multiplication, uses only real number multiplied by 2, operations less
divider
- 基于Verilog的除法器设计，可以直接在Q2里面运行哦~-Verilog-based design of the divider, which can be run directly in Q2 Oh ~
ADC_16bit
- VERILOG 16-bit Analogue-Digital Converter-VERILOG16-bit Analogue-Digital Converter
FFT
- 用VHDL语言建立了quartus工程，可进行dsp处理-VHDL dsp
CuFIFO
- fifo的vhdl代码,比较简单，适合初学。-fifo the VHDL code, is relatively simple, suitable for beginners.