资源列表
GPS_CA_CODE_GEN
- gps接收机码发生器原代码，已经在实际工程中得到应用。供大家参考。-gps receiver code generator source code, has been applied in practical engineering. For reference.
lcd16x2_ctrl
- lcd16*2初始化源码，verilog 可直接引用-lcd16*2 initialization
65_conditioner
- 空调系统有限状态自动机7 -failed to translate
myfifo
- fifo(1-6:1):using ip-code and rd wd interface-fifo:using ip-code and rd wd interface
eth_crc
- crc校验码Verilog 程序。此为4位并行crc——32校验。-crc checksum Verilog program. This is a 4-bit parallel crc- 32 check.
680605rece_7E
- hdlc协议的相关程序，用verilog语言编写，供大家交流学习-hdlc protocol procedures using Verilog language for the exchange of learning
Ths1207
- VHDL实现Ths1207控制器，根据硬件电路对THS1207进行配置，并读取AD转换结果。-VHDL implementation Ths1207 controller, according to the hardware circuit configuration of the THS1207, and read the AD conversion result.
crc32
- CRC32源码，已经在xilinx FPGA上验证，没有问题。-The CRC32 source has been verified in the xilinx the FPGA, there is no problem.
multiply_vhdl
- 用VHDL语言设计一款带进位的5位乘法器。-Design with VHDL into a 5-bit multiplier.
EXDTMF
- a C Programm for a DTMF pic16F8-a C Programm for a DTMF pic16F877
sync_srl_fifo
- 适合xilinx FPGA的同步fifo-Synchronous fifo for xilinx FPGA
division
- coding for division given in vhdl for integer division