资源列表
asynchoronization_FIFO_design
- 《Verilog HDL 语言编程》 异步FIFO设计（基于Verilog)
38yima
- 本文为用vhdl语言编写的38译码器，为doc格式，请先复制到相应软件例如maxplus中再使用。-This article was prepared by using VHDL language decoder 38 for doc format, please copy to the appropriate software such as maxplus in the re-use.
sht30
- 温湿度传感器sht30驱动，系统时钟为125M可读出温湿度。-sht30 driver,sysclk=125MHZ
8bitSINEGenerator
- 8BIT的正弦波波形发生器，用VHDL代码实现。
RS232_pro
- RS232 verilog coding 全参数化设计 可以自己设定波特率 时钟频率等 完全FPGA实现调通-RS232 verilog coding the entire parametric design can set the baud rate clock frequency of FPGA to achieve complete transfer pass
Altera_hello_led
- hello_flash是ALTERA的NIOSII核的标准程序。读写FPGA外带的Flash。-ALTERA the hello_flash is standard procedure for nuclear NIOSII. Hit-and-run of the FPGA to read and write Flash.
sdr_sdram
- sdram控制器顶层模块的VHDL源程序文件，可直接用-sdr SDRAM
keyBoard
- vhdl编写的4X4键盘扫描程序，可以有效的消除抖动，并且提供蜂鸣器输出。
counterN
- A Simple Register Counter in verilog Code with 8 bits
kongzhi
- 本程序为控制程序，在函数发生器的设计中它能够实现控制任一波形的输出，根据按键的选择来实现控制-The procedures for the control program, in the design of the function generator in it will be able to realize the control of any wave output, according to the choice of buttons to realize control
multiply
- Verilog hdl语言 常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
i2c
- 标准I2c读写时序，verilog Hdl-Standard I2c read and write timing, verilog Hdl