资源列表
wishbone_m4_s8
- wishbone 骨幹部份 RTL 源碼, 以verilog 寫成, 自創. 支源 4 master 及 8 slave-wishbone core, write by verilog, support 4 master and 8 slaver. language: verilog.
pci
- PCI9054接口程序，是自己写的，PCI9054的J MODE，在3e的FPGA上测试通过。-The PCI9054 interface program, write your own PCI9054 the J MODE 3e FPGA test passed.
20bitBINtoBCD
- 在50MHz时钟下实现自增计数并驱动6位数码管进行显示-50MHz clock and drive six digital tube display increment count
add
- The circuit 1 in is a 1-bit binary adder with 3 inputs (A, B and Carry-In) and 2 outputs (Sum and Carry-Out).The circuit 2 depends on circuit 1 which create a VHDL file ADD4 which is a 4-bit binary adder built using ADD1 components.
viterbi_decode_veeren
- Viterbi decoding algorithm
FPGA_SPI
- 本源码是用verilog语言编写的FPGA的SPI主机代码，可以用做SPI开发参考。-The source code is written in verilog FPGA SPI master code, can be used to develop a reference SPI.
cpu
- 本代码主要通过VHDL语言描述了一个CPU，包含了MAR,MBR,PC,BR,ALU,ACC等一系列寄存器。-The code is mainly described by VHDL language a CPU contains a series of MAR, MBR, PC, BR, ALU, ACC register.
a1
- 基于FPGA的B超数据采集功能，根据输入图像的束同步与帧同步信号，采用中断控制进入FIFO的图像数据的读写操作！-FPGA-based B-data collection capabilities, according to the input image beam synchronization and frame synchronization signal used to control access to FIFO interrupt the operation of image dat
lbs_fpga_upld
- 利用FPGA实现与powerpc的localbus数据接口代码。用verilog实现-localbus interface with PowerPC using Verilog
sdram_mdl
- 关于RS232串口调试中接收和发送的控制模块部分的程序-About the RS232 serial port receive and transmit debugging control module part of the program
UART
- 串行接口UART的用VHDL语言的简单实现，希望对大家有帮助
fifo_src
- verilog语言实现，利用BlockRAM实现FIFO。-Verilog language, the use of BlockRAM achieve FIFO.