资源列表
www
- 实现三位二进制数相乘,含有进位位，根据乘法的过程二得出-the design is aimed at three bit digital to multiply
icmp
- VHDL implementation of ICMP protocol tested
balucaidhengsheji
- 采用VHDL设计的八路彩灯设计，可实现四种不同状态的彩灯显示形式-This is a colourful led-light design which can realize different displayer of led-light
usb_device
- FPGA的一种实现usb设备通用方法，是nois的下的实现。-FPGA a usb device generic nois under implementation.
FreqCounter
- 一个有效位为4位的十进制的数字频率计,VHDL语言编写，已在硬件实验箱上实验通过。-an effective place to four the number of decimal frequency meter, VHDL language, in the box on the experimental hardware experiment.
uart_rar_testbenchfidsof
- code VHDL uart mode -code VHDL uart mode code VHDL uart mode
Rotorsystemcriticalspeedbeforethethird-ordermethod
- 汽轮机转子系统前三阶临界转速的传递矩阵法-Turbine rotor system critical speed before the third-order transfer matrix method
SpreadSpectrum
- spread spectrum function proce-spread spectrum function process
VHDL_FIR_PRO_scr.rar
- 可编程的FIR滤波器VHDL实现，只要输入FIR的阶数以及系数，就可在FPGA中实现FIR滤波器,Programmable FIR filter VHDL implementation, simply enter the order number as well as the FIR coefficients, we can implement FIR filters in FPGA
counter
- 用VHDL语言实现的计时器，最大计时为24小时，计时精度为1ms，设有复位和暂停功能，使用的晶振频率为50Hz。-VHDL language implementation of the timer with a maximum time of 24 hours, timing accuracy of 1ms, with reset, and pause functions, using the crystal oscillator frequency is 50Hz.
DDSVerilog
- Verilog 实现的DDS源码，可以配合NiosII软核使用 -Verilog realization of DDS source, you can use with soft-core NiosII