资源列表
一个波形发生器和sine波形发生器
- 这是一个典型的正玄波发生器程序和一个任意波形发生器程序，大家可以参考学习，对于vhdl入门还是很有帮助的-This is a typical wave generator Shogen procedures and an arbitrary waveform generator procedures, Members can take a learning portal for VHDL or helpful
FFT8
- FFT8，8点FFT运算，用verilog vhdl 语言编写，可以应用于64点FFT-FFT8, 8 点 FFT computation, using verilog vhdl language, can be applied to 64-point FFT
txt
- 老师上课的讲的程序 拿出来分享一下 关于电路VHDL语言的-Speaking teacher in the class to share out the procedure on the circuit VHDL language
campur
- total added value for 6 data in 32bit floating point for verilog code
jtag_master_latest.tar
- jtag 主机,根据jtag 标准协议编写的verilog代码-the jtag host, according to the jtag standard agreement prepared by the verilog code
jtag_master.tar
- JTAG模块的VHDL代码，用于了解JTAG内部结构原理，可集成嵌入IC,为IC提供JTAG功能。十分强大的代码，方便可靠。-VHDL code JTAG module is used to understand the internal structure principle JTAG can be integrated embedded IC, the IC provides JTAG functionality. The code is very powerful, convenient
24LC02B
- 微芯的24LC02B的IIC读写控制程序，经过验证有效- Microchip s 24LC02B official Verilog literacy program, proven effective
UPLOAD
- BASIC AND GATE OF 3 INPUT & 4,8 AND 16 DECODER
fifobaseddprammemory
- This file if about DPram based fifo storage... wirte and read in both ports
crossroadtrafficlights
- 十字路*通管理器设计，甲、乙道路交替通行，每次通行时间30s 交替通行时刻，要求有5s的准备时间，即每次绿灯变红灯时，黄灯应先亮5s。而红灯变绿灯则不需要亮黄灯 -Intersection traffic management design, A and B alternate access road, each turn of access time access time of 30s, 5s required preparation time, which changes eac
Six-story-elevator-controller
- 六层电梯控制器，这个很不错的，分享给大家-Six-story elevator controller, this is very good to share for everyone
4BCD
- 4个7段lcd同时显示的程序，已经在digilent的nexy2板上通过验证，非常好用易懂，适合初学者学习-display 4 leds