资源列表
双路脉冲发生器（veralog）
- Verilog HDL 程序 双路脉冲发生器的代码 包含了键盘控制，LED显示，脉冲发生，脉冲频率测量模块 是我自己写得，希望能对你有帮助，有问题可以mail：shaojunwu1@163.com-Verilog HDL dual-channel pulse generator procedure code includes a keyboard control, LED display, pulse, pulse frequency measurement module is wr
UC1697V
- UC1697V-带MTP功能 LCD驱动8080 Mode -UC1697V 8080 Mode
Nexys4_Master_ucf
- DIGILENT NEXYS MASTER UCF
vhdl.rar
- 一个很好用的串口的VHDL实现。。quartus2编译通过,Serial port with a very good realization of VHDL. . quartus2 compiled through
Altera_EPCS_Configuration_Device
- Protel99库Altera_EPCS_Configuration_Device-Protel99 Library Altera_EPCS_Configuration_Device
Coding
- 这是用VHDL语言编写的4位比较器，用了三种描述进行编写-This is the VHDL language with the 4-bit comparator, used to prepare three kinds of descr iptions
tv_csync_gen
- Generator of composite synchronisation TV signal on Altera DE2-35 board.
frequency_division
- 三分频电路是硬件工程师招聘中必考题目，看似简单却能够挂到很多人，这里给出三分频的VHDL设计，其他奇数分频电路均可以参考此分频设计。其中并附有简单的偶数分频设计-Here are three points frequency VHDL design, other odd points frequency circuit can refer to this crossover design.
Trafficlightcontrol
- VHDL code for traffic light control
Code1
- This is a code for wireless point-to-point communication using Altera FPGA and TI s CC2500 transceiver-This is a code for wireless point-to-point communication using Altera FPGA and TI s CC2500 transceiver
r22sdf_bf1
- Verilog Implementation of Butterfly 1 of R22SDF algorithm
ADC0809VHDL
- VHDL语言编写的程序，实现控制ADC0809的工作 -VHDL prepared by the procedures, the control Connection between ADC 0809