资源列表
new_128HZ
- 基于vierlog+maxplusII的频率合成器的设计与实现。比较好的代码。-Vierlog+ maxplusII based frequency synthesizer design and implementation. Better code.
2
- 进阶实验_02_抢答器 ：抢答器，4路-Advanced experimental _02_ Responder: Responder, 4
kcsj
- 利用Verilog层次化设计的多功能数字时钟，可以调时，设置闹钟，仿广播台整点报时(The use of Verilog hierarchical design of multi-functional digital clock, you can set the alarm clock, similar to the broadcast station, the whole point of time)
pwm4
- 用verilog编写的脉冲宽度调制器的FPGA工程-With verilog write pulse width modulator FPGA project
abs_mode
- abs_mode 2-complement souce and testbench code
61EDA_D1061
- fpga 串口通信 本程序在fpga开发板上实验成功-fpga serial communication program in fpga development board in this experiment was a success
Example-b3-1
- Altera 基础篇公司书籍源码
27_dds_wave
- dds test,基于FPGA的dds测试，很好的学习资料，大家都来学一学-is very good
Verilog-communication-source-code.RAR
- 基于Verilog的串口通信源码 ，实现串口通信功能-Verilog source code based on serial communication
fre_fenpin
- 一款非常实用的任意分频软件，可以产生代码在quartus ii 中使用，可调占空比，可以预览产生的图形-A very useful frequency of arbitrary software code can be used in the quartus ii, adjustable duty cycle, you can have a graphical preview
axi3_axi4_perfect
- 介绍AMBA，axi3 与 axi4的一些基本知识，并详细介绍了传输特性(Introduction to AMBA. Some features between axi3 and axi4 and transfer features)