资源列表
Final
- 乘法器,模拟两个0-99的数相乘，将结果显示在7段数码管上，可FPGA平台烧制~-Multiplier, two 0-99 multiplying the number of analog, the results displayed in the 7-segment digital tube, may FPGA platform firing ~
TR0114-VHDL-Language-Reference
- This comprehensive reference provides a detailed overview of the VHDL language and describes each of the standard VHDL keywords (reserved words)
08_uart
- fpga 串口程序，实现串口接收并自动发送-FPGA serial procedures, serial receiving and automatic transmission
DISP
- 基于VHDL的程序设计文档，模拟的地铁售票系统
DPLL
- 数字锁相环频率合成器的vhdl实现的源代码-Digital PLL Frequency Synthesizer vhdl source code to achieve
smc
- 时钟倒计时，可以很好的实现倒计时功能，已经验证，初学者很好的参考工程-Clock countdown, countdown function can be well implemented, has been verified, a good reference work for beginners
tutorial7
- spartan 3e-counter lcd vhdl code u can use ise 9.2
Comparator
- VHDL Bit Comparator
单周期CPU实验报告
- 单周期CPU的设计思路(包含数据通路、指令集、信号的设计)(Design Ideas of Single Cycle CPU)
FIRDesign
- FIR Design implementation in VHDL.
singlecircle_cpu
- 实现十一条指令的单周期处理器，运用Verilog语言，顺利执行，仿真正确。-To achieve single-cycle instruction processor XI, the use of Verilog language, the successful implementation of the simulation is correct.
SRAM
- 利用程序实现SRAM_读写测试，先进行初始化，读写操作，里面的页操作和bank操作。-Using program SRAM_, speaking, reading and writing tests, first initialized, read and write operations, the inside of the page and bank operation.