资源列表
TRDB_DC2
- DE1/DE2CCD摄像头Verilog源代码。-DE1/DE2CCD camera Verilog source code.
current_measurement
- 这是一个实现了无刷直流电机闭环控制电流环检测的程序，一起还有滤波器的使用。性能良好。为个人原创-This is a realization of the closed-loop control of brushless DC motor current loop detection procedure, also with the use of filters. Good performance. Be original
Tym605V2Demo
- FPGA（赛灵思）试验箱 实验程序 有Audio,Buzzer,key,ledarray,ledseg-FPGA（赛灵思）试验箱 实验程序Audio,Buzzer,key,ledarray,ledseg
pingpong
- 用verilog实现的乒乓球游戏，在spartan3a系列FPGA上运行成功，支持两人对战-pingpong game using verilog,tested on spartan3a board,support dual mode
Exp25_USB_Reader
- 基于FPGA与Nios II设计的USB电子文本阅读器-Nios II FPGA-based design with USB electronic text reader
ASIC-Design-With-Synopsys
- ASIC Design With Synopsys
YL9200_Test
- 9200 带CAN 带VGA全部源码，难得-9200 with a CAN with a VGA all the source code, a rare
xp
- 96pin连接器、3366电位器、67148_AD_AD537、AD202隔离放大器、AD537、AD650SD电压频率,频率电压转换器、AD1671高速AD、AD7376,128位数字电位计、ADR440_441_443_444_445、CA3140高输入阻抗运算放大器、EPM7256,FPGA、IC封装大全、IRF430功率场效应管、LH0070、LM139四路差动比较器、MAX197、PCA82C250[1]、Pt1000、TD823高温功率放大器、TD823高温功率放大器、固态继电器AQ
uart_rx_tx_ok
- 用于串口的接收和发送，不含校验位，直接将串口接受的数据进行发送，实现多字节发送和接收-It means for receiving and transmitting, excluding parity bit serial port, the serial data received directly transmitted, multi-byte transmission and reception
数字钟
- fpga课程中用vhdl语言编写的数字钟 输出到板子上是，就是一个数字时钟
digital-colok
- 用quartusII编写的vhdl代码，在板子上输出的显示就是数字钟，也可以重置、设置时间。-With written in VHDL quartusII code, the output is the digital clock is displayed on the board, you can also reset, and the time.
ASIC_VHDL_FPGA_design_lectureNotes
- 这是美国普渡大学（Purdue University West Lafayette)ASIC design 的课件完整版！带事例和讲解的非常好的VHDL学习材料！含有vhdl 基础知识，设计步骤，UART, RTL,Test Bench 以及测试和调试，DEBUG等各种VHDL设计者必学知识！-This is Purdue University (USA) ECE 337 ASIC design class lecture notes! very classic! The content inc