资源列表
VHDLlearning
- 学习VHDL期间的课件，介绍了入门的基本知识，还有一些实例，希望对大家有用。-Learning courseware during VHDL, Introduction to the basic knowledge presented, and some examples, we want to be useful.
logic_new3
- verilog简易逻辑分析仪2003年全国大学生电子设计大赛，仪器仪表题-verilog logic
lab08_web
- 实用的程序代码，希望对大家有用，已经调试通过
NIOSII_de2
- 基于SOPC的FPGA系统设计，测试数码管、LED、液晶显示屏，整个系统在DE2上运行通过，使用的是Quartus 6.1套件-FPGA-based SOPC system design, testing, digital tube, LED, LCD display, the entire system run by the DE2, using Quartus 6.1 Suite
DE2_Default
- 自己编程的采用verilog语言实现的关于altera的DE2-70开发板的一个实用程序，实现的是自动售货机的找零功能-Own programming language used on the altera verilog the DE2-70 development board of a utility, to achieve the change for vending machines function
25_ov7670_lcd
- verilog ov7670 捕捉和显示-Verilog ov7670 capture display
memory
- DESIGN A SINGLE PORT MEMORY 8*256 using array with standard logic & tri_state gate, and simulate it by reading & writing word
fft_IPcore
- 如题 基于FFT的ip核系统程序 经测试好用-Such as the nuclear issue through FFT-based test easy to use ip
AlteraFPGACPLDcoder
- Altera FPGA/CPLD设计（基础篇）随书代码-Altera FPGA/CPLD design (fundamental) with the code book
the_last
- VHDL语言实现两个人掷骰子游戏，最多6次，大者胜则结束游戏并在点阵上显示，一直平手则一直进行直到达到6次。-Achieving the dice game between two people by using VHDL language.The maximum number of times is 6.The game will over when there is a biger one in one time,otherwise,the game will continue until
fir_filter_50Mhz
- 基于并行分布式算法的高速Fir滤波器的设计代码，采用Verilog编写，压缩包为quartus II编译过的工程代码-Parallel and distributed algorithms based on a high-speed Fir filter design code, Verilog prepared, compressed package for the quartus II compiled project code
xsp605_ilinx_mig_ipcore
- 赛林思开发板sp605的内存管理单元的ip核调试通过-SP605 IP core mig