资源列表
mjpeg-decoder_latest.tar
- 基于fpga实现的硬件jpeg格式图片的解码器-jpeg decoder based on FPGA
or1200_sopc
- 用verilog语言编写的or1200+wishbone总线+串口uart+片上ram，最小系统soc。包括片上ram的软件系统（C语言编写）都有。但下载者要使用此系统需要很多工具链，搞soc的应该都装好了。 绝对原创！用quartusII11.0在Altera DE2-115上验证通过，Modelsim SE 6.5f仿真通过。-It s very strange for Chinese people communicating with each other in English. Ri
dpim_circle
- dpim是光通信中使用的一种调制方式，这里提供的是它的环回代码，自己可以根据需要拆开了下载到两块板子上。-dpim is used in an optical modulation, here is its loop-back code, they can download needed two apart on the board.
openmsp430_latest.tar
- 开源的MSP430 Verilog源码，供学习使用-Open Source MSP430 Core verilog code, for studying.
lzr
- 精简指令计算机设计,verilog语言,
cycloneIII_dev
- cycloneIII_3c120_dev_kit-v7.2.3_CDROM cycloneIII_3c120开发套件的全部CD资料-cycloneIII_3c120_dev_kit-v7.2.3_CDROM cycloneIII_3c120 all the CD information Development Kit
Logic_With_VHDL
- this doc explains logic with vhdl
数字信号处理的FPGA实现(第4版)源码
- 数字信号处理的FPGA实现(第4版)的配套源码，极具参考价值。(The source code of the realization of digital signal processing on FPGA (4th edition) is of great reference value.)
jisuanjiaihaozhe2010nian
- 计算机爱好者2010年12期的杂志，希望广大计算机爱好者能够喜欢。-Computer enthusiasts 12 of the magazine in 2010, I hope the majority of computer enthusiasts to enjoy.
SRIO_DSP_X1
- xilinx 7 系列fpga与dsp srio数据传输(fpga and dsp communation with srio)
e011_timingdesigner
- FPGA时序设计时必备的软件。可以有效的提高逻辑设计的速度，调整设计时的时序。-FPGA design timing necessary software. Logic design can effectively improve the speed of adjustment of the design timing.
fpga
- 关于FPGA的相关介绍与一些例程代码实现2(About FPGA related introduction and some routine code implementation)