资源列表
FIFO
- 将ROM的正弦波数据输入FIFO存储器，然后输出，有modelsim仿真波形-Verilog FIFO ROM mif sine
FPGA-Develop
- 张国斌老师力作，指导初学者迅速入行，工程师可以获益匪浅，避免低级错误。-The Guobin teacher masterpiece, to guide beginners quickly into line, and engineers can benefit from, to avoid low-level error.
pg_070731
- 基于fpga的屏幕测试程序，可以根据测试要求在上位机的控制下生成各种图形图像，并调整参数
miaobiao
- 数字电路课程设计，原理图实现设计一个电子秒表-Digital circuit design, schematic design to achieve an electronic stopwatch
wARM
- 著名的wARM源代码，作者吴瑞祥，Verilog HDL源代码。(Famous wARM source code, author Wu Ruixiang Verilog, HDL source code.)
xyy
- 基于FPGA的vhdl语言的波形发生器材料及工程代码-FPGA VHDL language-based waveform generator materials and engineering code
dianlidianzijishu
- 电力电子的论述及其应用展望论述和应用前景-Discussion of power electronics and its application prospect and prospect discussed
GHDL
- quartus等文件业余爱好者测试仿真工具教程GHDL英文网站-quartus other documents amateur test simulation tools tutorial GHDL English website
blank
- 监控摄像头传入数据，通过芯片TVP5150转换成数字信号，其中sav_check.vhd检测帧头，converter.vhd将信号转换成Y，Cb，Cr格式，最后write_blank.vhd重新组建完整数字信号，最后通过ADV7171转成模拟信号输出到监视器上。这中间，可以对Y做各种图像处理，如滤波处理，均衡处理，只需要在converter之后添加处理文件即可。-Surveillance camera incoming data through the chip TVP5150 converte
10_uart
- 在quartus ii开发环境中实现了uart串口通信模块的控制功能，经测试，该模块能产生正确地时序，功能与预期功能一致。-In quartus ii development environment to achieve the uart serial communication module control functions have been tested, the module can generate correct timing, functionality consistent w
FIFO
- FIFO先进先出，控制时序，对urat、SDRAM、DAC等时序理解都有帮助-FIFO FIFO control the timing of urat, SDRAM, DAC and other timing understanding have helped
I2C_xo
- IIC的verilog源码，可以在Lattice的XO DEMO板上运行的IIC代码。内附说明文件-IIC' s verilog source code, you can Lattice' s XO DEMO board to run IIC code. Included documentation