资源列表
FPGA+DSS+UART
- 用FPGA实现任意波形发生器的源代码，另外还包括FPGA实现UART，从而与MCU实现串行通信。
adpll
- 全数字锁相环 功能与74297相同 提供参数配置
booth
- 8位改进型booth算法的verilog源代码-8bit booth verilog
sin_10M
- FPGA/cpld 产生步进为1Hz的正弦波,最大为10M,使用的晶振为50M -FPGA/cpld generation step of 1Hz sine wave, up to 10M, 50M crystal oscillator for use
prng
- 采用线性同余法的素数模乘同余发生器产生随机数,采用5级流水线设计-Using a linear congruential method prime modulus multiplicative congruential random number generator, using five pipeline design
MedFilter_VHDL
- 用VHDL实现了Matlab中MedFilt1函数3阶中值滤波。进行排序时没有用软件使用的排序法，而是通过简单的比较实现。-VHDL implementation using the Matlab function MedFilt1 of 3-order median filter. Sort of no use when the software used to sort the Law, but through a simple comparison of implementation.
all_MedFilter_VHDL
- 本文介绍了中值滤波算法的FPGA详细实现，很详细，很全-This article describes the median filter algorithm to achieve the FPGA detailed, very detailed, very full
Infrared-emission-receiving
- 该程序是红外接收程序，是由汇编语言编写，可在单片机的最小系统上运行。-The program is an infrared receiver program is written in assembly language can be run in the smallest single-chip system.
lcd_drv
- LCD driver for 2-lines LCD displays with controller
ffcsr
- 伪随机序列产生器－filtered 代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.
LIFO
- LIFO，先进后出缓冲器（栈），verilog源代码，包括测试代码。-LIFO, last-out buffer (stack), verilog source code, including test code.
denoise_tb
- 基于Bayer算法的图像实时采集去噪处理的仿真实现方法-Simulation of Real- time Image Denoising Based on Bayer Algorithm