资源列表
dzzh
- eda课程设计:数字钟--vhdl语言全部源代码
my_design_frequency
- 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号是最重要的信号之一。 下面我们介绍分频器的 VHDL 描述，在源代码中完成对时钟信号 CLK 的 2 分频， 4 分频， 8 分频， 16 分频。 这也是最简单的分频电路，只需要一个计数器即可。-in digital circuits, and often the need for higher frequency for the clock frequency operation, th
VHD
- 低电平脉冲状态的捕抓（多个）缓存并 用减小的并口线输出
ztj
- max+plusII下的使用列举类型的状态机-max plusII use of the listed types of state machine.
Full_adder
- 全加器的VHDL逻辑编程，外加两个全功能，这个过程有些简单，但可能有一些初学者的帮助。-Full adder VHDL logic programming, plus two full-function, this process some simple, but there may be some beginners help.
ChkRpm
- Motor RPM checking source code
sumador_divisor
- suma dos señ ales y las divide entre 2
trivium
- trivium密码算法的 verilog 实现 测试正确-trivium password algorithm verilog test correct
DBounce
- Using mechanical switches for a user interface is a ubiquitous practice. However, when these switches are actuated, the contacts often rebound, or bounce, off one another before settling into a stable state. Several methods exist to deal with this te
mux
- 使用VERILOG實現多工器之設計,並附上tb供測試-VERILOG realized using multiplexer design, along with tb for testing
pci
- PCI硬核源代码,支持33.3M的时钟频率,支持IO模式和内存模式的PCI操作-PCI operation of the the PCI hard core source code, support 33.3M clock frequency to support IO mode and memory mode
dds_clk
- VHDL代码实现FPGA中DDS功能，输出频率可调-VHDL code for the FPGA DDS function, the output frequency is adjustable