资源列表
latch
- 门拴电路,4位选择器，alu,用verilog写的。-doors Shuan circuit, four selectors, ALU, with Verilog writes.
add_1p
- 数字信号处理的fpga实现，用VHDL编程设计加法器-Digital signal processing to achieve the FPGA with VHDL Programming adder
test4
- 用 vhdl 语言实现的 32个 条目的 ARP-using vhdl language to realize ARP protocol with 32 entries
VIDEO_AD_8V
- SC9766视频采集芯片，双通道，工作频率25M。-sc9766 verilog
viterbia
- 实现viterbi译码，通过比较最小汉明距来判别最佳路径，删除不必要的路径，最终找到最佳路径。-Implement viterbi decoding, by comparing the minimum hamming distance to distinguish the best path, delete unnecessary path, finally find the best path.
floating_point_adder
- 该代码描述了一个浮点加法器的功能，浮点格式采用IEEE标准-The code describes a floating-point adder function, the use of IEEE standard floating-point format
fpu_sub
- verilog code floating point subtraction
mult
- 用verilog HDL语言实现的16位乘法器，以及tesrbench（测试文件）。-Verilog HDL language with 16-bit multiplier, and tesrbench (test file).
SSD_MULTIPLEXING
- four seven segment displays are in multiplexing implemented on xilinx FPGA XC3S50
agc_gen
- AGC(自动增益放大) Verilog代码 设计可以参考-AGC (automatic gain control) can refer to the Verilog code design
CrossClockDomain
- 跨时钟域设计不错的设计，进过modelsim仿真通过。-Cross-clock domain design is good design been to modelsim simulation through.
fast_antilog_latest.tar
- 运行速度不如我的日志代码：166MHz，对于日志的250MHz。 注册输入会带来。 采取与日志相同的资源。-Doesn t run quite as fast as my Log code: 166MHz, vs. 250MHz for the log. Registering the input would bring that up. Takes about the same resources as the log.