- ywjm 有移位算法编写的一个加密原代码
- Kalman[1] 介绍卡尔曼的资料 入门
- ZLG7290B_app FPGA整个板子开发板电路原理图
- namednodemapsetnameditemns05 Retreive an entity and notation node and add the first notation to the notation node map and first entity node to the entity map. Since both these maps are for readonly node
- cyfypt VC写的程序启动时的窗口风格
- 7633282 XP形式的窗体
资源列表
16szxgq
- 16位数字相关器，通过4个4位相关器和两级加法电路组成
door_state
- 实现自动门的控制,实现其开、关、复位、门开最大、门关最小等功能-Realization of automatic control
binary_to_BCD
- 本人编写的2进制转换为BCD码的verilog程序，绝对可用，已测试通过。-I write binary to BCD verilog program, absolutely free, have been tested.
counter
- 脉冲上升或下降沿个数计数功能，并且可以配置初态和触发计数条件-Pulse rise or fall along a counting function, and can be configured to initial and trigger conditions
cmi-decode
- cmi decoder,veilog代码，已验证-cmi decoder, veilog code has been verified
shifter2
- 改进型桶式循环移位器，用VHDL实现，经时序仿真测试正确-modified barrel cyclic shifter by vhdl
synd
- Syndrome calculator basic unit for reed solomon decoder in verilog language
REG8
- 寄存器的VHDL源码.可能有点简单 新手大家间量 希望和大家学习-VHDL source register. May be a bit simple volume between novice you would like to learn
file_io
- 读写硬盘文件的VHDL仿真例程，该例程能够帮助FPGA设计人员读取硬盘的数据文件输入仿真环境，并且将仿真后的数据存入硬盘-test bench for reading and writing disk files
vsim
- multiplexer 16_1 is a multiplexer with 16 inputs and 1 output.
decision_reg.vhd
- Variable register example
PWM-LED
- 根据输入电压改变pwm来调节LED输出光。-adjust PWM to dim LED according to input voltage.