资源列表
generate语句的应用
- vhdl实验 计数器：generate语句的应用
MECEditDocument
- 一个很好的基于单片机频率计的程序，希望对用的着的朋友有所帮助-A good frequency meter based on SCM procedures, hope to use a friend' s help
binary
- binary state machine encoder
mo12_counter
- 基于FPGA的VHDL程序实现模12计数器-FPGA VHDL model12counter
di1
- 计数器的设计，可以累加计数。实现计数功能，代码功能如下所示。-Count-counter design. Counting function, the function of the code is shown below.
inout-vhdl
- c p u 读inout 端口的vhdl 程序-Read inout port vhdl program
encoder
- RS(7,3,4)，码长七位，信息位三位，纠错位四位，经过验证成功-RS (7,3,4), the code length of seven, three of information bits, bit error correction four proven successful
pwm_task_logic
- 脉冲宽度调节（pwm）的verilog源码-Pulse width modulation (pwm) the verilog source
LFSR
- Verilog code for an 8-bit LFSR
uart_trs_state
- 本程序是串口的FPGA产生程序，希望在此能够给与大家共享-This program is a serial FPGA generator, I hope to give everyone shared this
fulladder
- this is fulladder 1bit with testbench
pwm
- 使用VHDL实现可调的PWM控制器，便于初学者学习-Use VHDL to achieve an adjustable PWM controller, easy for beginners to learn