资源列表
testbench模版
- testbench测试模版
33_COMP
- vhdl做的实数比较器，比较简单，但是实用-The real number vhdl comparator, is relatively simple, but practical
DDS
- 基于fpga技术，采用DDS原理产生3MHZ的正弦波。 -Produced with the DDS sine wave 3MHZ.
Counter24VHDL
- 用VHDL语言实现24进制计数，具有清零、控制使能作用。-VHDL language with the binary count of 24, with clear control in enabled.
VrRAM
- 一个简单的RAM设计，包含内容不多，是一个RAM的精简体，可做学习之用-A simple RAM design, including the content much, the essence of RAM is a simplified, to do with learning
lcd-display
- 七位段码显示模块，采用自顶向下的编程模式，共三个开发程序-Seven segment display module, using top-down programming model, a total of three development programs
vote7
- 实现七个人投票，超过四个人投票通过，否则不通过-Achieve seven votes, more than four people voted, or not through
DEM_NP4BIT
- 4-bit binary count up
traffic
- 实现4种状态的交通灯控制，延时，以及各种可以实现的功能 -To achieve the state of the four kinds of traffic light control
sw_leds
- 精简指令cpu设计，外扩电路设计，led开发板驱动-wb_sw_leds，opencore，risc cpu design。
adder
- Adder vhdl code 8bit from a project i did last week
divby3.v
- This Divider by 3.-This is Divider by 3.