资源列表
adder44
- adder 4 + 4 bits, for use with a Altera, and 2 displays 7 segments-adder 4+ 4 bits, for use with a Altera, and 2 displays 7 segments
clk_gen
- 基于fpga的分频器的vhdl描述，可以直接调用，只需修改一些参数-Fpga based on the divider vhdl descr iption, can be directly called, simply changing some parameters
SPI_Port
- VHDL 实现SPI接口、并行数据输入，SPI接口数据输出。-VHDL to implement the SPI interface, the parallel data input, SPI interface data output.
Hex_decoder_7seg
- 十六进制显示译码器，VHDL语言的设计，根据高低电平的变化进行数码管的数字显示-Hexadecimal display decoder VHDL language design, high and low changes in the number of digital tube display
sine
- 简易的正弦信号发生器，用verilog代码写成-A simple sinusoidal signal generator, written with verilog code
reg2
- Register2 Project VHDL
clkdiv
- 占空比可调 分频系数 都可随意设定的分频器，语言为Verilog HDL-Duty cycle factor can be freely adjustable frequency divider set the language for the Verilog HDL
aahr
- vhdl下编写的rom,vhdl专用这个编程能帮你学习到老-it s very good!when you download this one ,it s good for your study
di3
- IP核和乘法运算模块分别有两个输入端口a、b和clk时钟脉冲信号及一个输出端口p，用例化语句将这两个模块合成一个乘法器后就生成了由两个输入端口a、b和clk时钟脉冲信号及两个输出端口p1、p2组成。-IP cores and multiplication module respectively, the two input ports of a, b, and clk clock signal and an output port p, these two modules with the in
matlabtomodelsim
- matlab to model sim converter coding of vhdl code ypu want to convert that matlab into the xilinx platform model sim simulator
laser_timer
- laser timer source and test bench code 4
Stepper-motor
- 步进电机驱动模块设计，使用硬件描述语言设计。-Stepper motor driver module design, using a hardware descr iption language design.