资源列表
15th_counter
- 用VHDL实现15位计数器,可应用于FPGA,ASIC的开发和应用-VHDL implementation with 15-bit counter can be used for FPGA, ASIC development and application of
paomadeng
- FPGA led实现8个跑马灯四个模式的装换-FPGA led Marquee
Clock_Edge
- The Audio Core interacts with the Audio CODEC (enCOder/DECoder) on the Altera DE2/DE1 Boards and provides an interface for audio input and outpu
fir
- vhdl code for fir filter
adder_32
- 32bits 加法器-32bits adder
UART
- pic16f4011 实现异步通讯，可以直接用-pic16f4011 UART
lineardecoder
- 7,4汉明码的译码程序，条理清晰，易读易懂-7,4 Hamming code decoding process, the clarity, easy to read and understand
test_proiect_MCeas
- test m ceas. este un ceas. ceasul are minute ore secunte.
Tristate_driver
- it contain source code for tristate driver module.
thermometer-control
- this a digital thermometer control program using 8051 micro controller and LM35 temperature sensor-this is a digital thermometer control program using 8051 micro controller and LM35 temperature sensor
Uart_2
- ＳＴＣ单片机的串口模块可以采用Ｔ１定时器作为它的波特率发生器，同时其内部也集成了一个独立波特率发生器作为串口的波特率发生器，本例子采用的是常用的独立波特率发生器ＢＲＴ作为它的波特率发生器-STC microcontroller serial port T1 timer module can be used as its baud rate generator, while its interior also incorporates an independent Baud Rate Genera
clk_div3.5
- 用VHDL实现的带清零的3.5分频的代码。调试通过。-Implemented in VHDL with a clear frequency of 3.5 code. Debugging through.