资源列表
EDAadd
- 全加器Full adder schematic waveform diagram(Full adder schematic waveform diagram)
1
- flv的vhdl教学文件:在线调试 自己慢慢欣赏吧-flv file of VHDL Teaching: Online debug their慢慢欣赏吧
evodem_mppt_son_hali_OK
- This my complete simulink project using xilinx system generator blocks. There is a buck converter and a control unit for FPGA calculating MPPT to get maximum power from the PV panel. MPPT calculation is done using sysgen blocks. Also HWCOSI
vhdl
- 数字逻辑设计语言vhdl 经典简明教程 包括简介、入门教程、实例分析-Vhdl digital logic design language, including the classical simple tutorial introduction, Tutorial, Case Study
key_led
- verilog hdl按键控制灯代码 用按键控制哪个led来亮灭功能-Button control lights Codes
Latch_sram
- FPGA内部集成RAM和锁存器模块设计，欢迎大家来验证-FPGA internal RAM and latches integrated module design, welcome to verify
Embedded_Design_Programming
- This book combines Simulink for high level programming and SystemC for the low level software development. This approach is illustrated with multiple examples of application software and MPSoC architectures that can be used for deep understanding of
BlockRam
- 块状ram使用实例，实现深度和宽度可调的FIFO，buffer。-The block ram instance, depth and width adjustable FIFO, buffer.
fasongjieshou
- fpga上发送模块和接收模块的设计与实现。不同的波特率-Design and implementation of the sending module and receiving module on fpga. Different baud rate
NiosII_SPI_bus
- 采用altera公司EP3C系列芯片实现的基于Nios II的SPI总线设计，采用Verilog编码-Altera company EP3C using the Nios II series chip SPI bus-based design, using Verilog coding
基于FPGA的简易CPU程序
- 基于FPGA的简易CPU程序，可完成连乘或连加等程序
ad706_verilog
- AD706在Sparten6使用的FPGA代码，测试通过-AD706 FPGA Code In Sparten6