资源列表
VERILOG-Simulation
- This VERILOG simulation example shows a 16 bit group ripple adder circuit for FPGA. The netlabel is used to split 16 bit bus to four 4 bit bus and connect them to four 4 bit adder. The result is joined to a 16 bit bus using netlabel. The Simulation c
ISE_lab17
- VHDL语言实现正选信号发生器，并仿真验证的源程序及代码-VHDL language is selected signal generator, and simulation and verification of the source code
ISE_lab17
- FPGA experimental program xilinx company s previous software -FPGA experimental program xilinx company s previous software
ISE_lab17_sinsignal
- 正弦信号发生器，excd-1竞赛开发学习板上实现 逻辑比较清晰-sin signal generator
32registergroup
- VHDL MIPS 32位寄存器组的设计-VHDL MIPS 32-bit register set design
UART
- 进阶实验之UART串口，波特率115200，与PC通信，用verilog写的-Advanced experiments UART serial port, baud rate 115200, and PC communications, written with verilog
sin
- 函数信号发生器，采样深度64，最佳工作频率1K--100KHz-Function generator, sampling depth 64, the best frequency 1K- 100KHz
wf1
- dds信号发生器，基于fpga的信号发生器，拥有基本的功能，是本人亲自编写，具有良好的稳定性和健壮性！我喜欢这个代码-dds signal generator, signal generator based on fpga, with basic functions，
Vme_Interface
- 这是本人设计的一个关于VME总线接口的FGPA程序，FPGA一边连接ARM LPC2294，一边连接VME总线，FPGA采用的XILINX公司的SPARTANII系列，程序包包含完整的工程文件-This is my design of a VME bus interface on the FGPA procedures, FPGA side of the connection ARM LPC2294, while connecting VME bus, FPGA using the XILINX
pinlvji
- (FPGA Verilog)测量频率、周期、脉冲宽度 -(FPGA Verilog) measuring the frequency, period, pulse width
Riple-TimeQuestTestbook.ZIP
- Quartus TimeQuest非常好的教程,by Riple.中文.
VHDL_FPGA
- 学习FPGA的好资料。适用于初级读者。其中既有硬件部分，又有软件部分-a program for learning FPGA