资源列表
multi_cpu
- 用xilinx ISE 14.3开发的多周期CPU系统，开发语言为verilog HDL.仿真调试与实际测试均已通过-Using xilinx ISE 14.3 development of multi-cycle CPU system, development language for verilog HDL. Simulation debugging and practical tests have passed
DS18B20_ysd
- 在quartusII下开发的DS12B20_vsd的verilog程序，方便大家的学习。-Developed under the quartusII DS12B20_vsd the verilog program to facilitate everyone' s learning.
Lab5
- 此為VHDL之非同步觸發、清除之單擊電路與同步觸發、清除之單擊電路設計-This is a non-synchronous triggering of VHDL, click to clear the circuit and synchronization trigger, click to clear the circuit design
absolute2relative_coding
- ISE编程仿真DPSK中相对码和绝对码的转换-DPSK code conversion relative and absolute code
ADCcaiyang
- 用Verilog HDL实现ADC采样。-Stepper motor control using Verilog HDL. Can the intelligent control speed.
verilog_pli
- pli函数在verilog中大量应用，但介绍pli的资料并不多，压缩包中的文档是我搜集的pli的资料，希望有对你有帮助。-Pli system fuction is used in verilog language, but material related pli in domestic is rare. the rar package is my collection on pli , hop it is useful.:)
FPGA
- 一些verilog语言程序，可在板子上实现流水灯，计数，按键等功能。-Some verilog language program, can be achieved on the board flowing water light, count, buttons, and other functions.
pingpang_ram
- 乒乓RAM静态随机存储器的控制，用于解决数据流连续存储问题。-Ping pong RAM static random access control, to solve the problem of continuous data flow storage.
PicoBlazeKCPSM3
- PicoBlaze KCPSM3处理器版本的基础指令介绍以及基本使用方法-Introduction of the PicoBlaze KCPSM3 basic instruction processor version and the basic use
ADC
- ADC IMPLEMENTATION IN FPGA
FPGA_UART
- 毕业论文2010届06电子(的“基于FPGA的UART模块设计”-what is this
Lab1~3
- 此為VHDL之暫存器、栓鎖器、三態匣、計數與除頻電路以及時脈產生電路-This is a register of VHDL, Latch, tri-state box, count divider circuit and clock generator circuit