资源列表
dds
- 在quartus软件上，采用verilog实现DDS功能。- using verilog realize DDS function On quartus software.
opencore
- 基于FPGA的视觉采集系统的实现，verilog源码-FPGA-based visual collection system, verilog source
CPU
- 使用VHDL语言实现了一个两级流水线的CPU，-VHDL language using a two-stage pipeline of the CPU,
CHENGXU
- 程序实现的功能是在一个8*8的数码管上实现汉字滚动实验。程序已经测试过了。-Realize the function is in an 8* 8 digital tube experiments to achieve Chinese scroll. Program has been tested.
XC3S700_HS_SDRAM
- 红色飓风3S700AN开发板SDRAM测试例程-Red Hurricane 3S700AN development board SDRAM test code
ml605_fmc_xm104_ibert_rdf0066_13.1_c
- ML605_Reference_Designs:ml605_fmc_xm104_ibert_rdf0066,xilinx开发板的fmc设计例程，包括源码和下载文件-ML605_Reference_Designs：fmc codes and download files include ace and bit file
fpga_spi
- 文件中包含有用fpga实现isp接口的源码，以及和处理器接口，测试时处理器是ARM7。-document contains useful fpga achieve isp Interface source, as well as the processor interface, testing is ARM7 processor.
filtro_hdlcoder
- Example project of a filter designed in MATLAB and exported to VHDL.
基于FPGA的音频驱动WM831+FIR滤波器
- 基于FPGA的音频驱动WM831+FIR滤波器
DE1_i2sound
- DE1开发板案例，开发板附带代码DE1_i2sound.rar -DE1 development board case, the development board with the code DE1_i2sound.rar
shifter32
- 32位桶形移位器，verilog语言书写-barrel shifter
dds
- 通过查表法，用FPGA实现波形的输出。预先将数据存放在ROM中，依次读取数据并输出。-Look-up table method, the output waveform with FPGA implementation. Advance to data stored in ROM, in order to read data and output.