资源列表
watch
- verilog 完全集合了电子表所拥有的功能，计时，调时，秒表，闹钟四个功能-verilog completely owned by a collection of spreadsheet functions, timing, tone, the stopwatch, alarm clock features four
src
- altera 的 fpga 中 fir实现示例，vhdl源码-fpga implementation of fir sample
IterativeDecodingofBinary
- In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and deco
DE2_WEB_QII_51
- ALTERA官方板子DE2官方代码，芯片是EP2C35F672C6N，官方历程(ALTERA official board DE2 official code, the chip is EP2C35F672C6N)
LCD1602
- 用Verilog写的LCD1602液晶显示，算法简单，程序稳定-Written in Verilog LCD1602 LCD, the algorithm is simple, stable program
LPM_VHDL
- VHDL编程时如何直接调用LPM参数化元件？-How to use LPM in VHDL?
TrackingPresentation_jon
- presentation a low cost video tracking algorithm implemented on an Altera DE2 board with Cyclone II processor. System uses a VGA controller and several SG-DMA s-presentation on a low cost video tracking algorithm implemented on an Altera DE2 board wi
PC_FPGA_Communication
- 本软件利用串口实现了电脑和FPGA的通讯。采用vhdl。就是为了FPGA开发的基础软件。-This software uses serial port to realize the communication between computer and FPGA. Using vhdl. this is the basic software to develop the FPGA.
Verilog_COMPLEXCLOCK-v2013.10.07
- 电子钟，闹钟，秒表，可调时间，采用6位数码管显示-Electronic clock, alarm clock, stopwatch, adjustable time, the use of six digital tube display
referee-partner
- 一种能够将多种球类（足球，篮球，网球）的计时、计分和重要数据记录等功能综合在一起的VHDL程序。-referee partner.
verilog-radix4
- Master Thesis(FFT_RADIX-4)-This thesis deals with a 64-point Radix-4 in-place FFT, based on an improved FFT algorithm. The whole FFT structure was implemented based on self-designed modules and by manipulating the embedded Virtex II FPGA’s module
oc8051.tar
- 8051 core writen in VHDL, fully functional and tested