资源列表
FIFO2
- 用verilog HDL语言编写的fifo存储器源文件 -Using Verilog language HDL FIFO memory source file
ps2_soc1
- ps2 keyboard controller
FIFO_EMIF.rar
- 实现FPGA通过EMIF总线给DSP定期发送数据的功能,FPGA implementation through the EMIF bus regularly send data to the DSP function
Digital-Clock
- 基于FPGA 的数字时钟SHEJI-Digital Clock in the FPGA
02_FPGA_Emulation_ITRI
- FPGA Emulation guide with EVS6 FPGA Board
Keyboard-and-mouse-Verilog
- Keyboard and mouse-Verilog
keyboard_ps2_verilog
- 键盘鼠标的原代码,用FPGA实现,使用Verilog HDL编写,已经使用FPGA验正过了,完全可以用-keyboard and mouse of the original code, using FPGA, using Verilog HDL preparation, already in use FPGA-mortem is over, it can be used
CycloneIII_SB_3C25
- Altera的CycloneIII Start Board,使用的PFGA是3C25，包括原理图和PCB，用Cadence Allegro打开-Altera
millisecond_counter
- 基于Spartan6写的fpga秒表，可以在七段译码管上显示，而且用按键来实现秒表的计时开始，停止，累加。而且该项目是移动信息工程学院的课程项目之一，希望对有需要的人有帮助-Fpga based Spartan6 write stopwatch that can be displayed on the seven-segment decoder pipes, and use the keys to achieve the stopwatch start, stop, accumulate. An
LabVHDL_10-12
- fpga clock alarm time-fpga clock alarm time
magnetic_stepping_motor_control_system
- 步进电机位置系统 步进电机位置系统block symbol file 步进电机位置系统的Verilog HDL程序设计 已编译通过
i2c controller
- a source code for I2c written in vhdl