资源列表
Verilog数字系统设计教程(第2版)
- 适合学习fpga的童鞋们，verilog语言数字系统设计，一本很不错的学习资料。(Suitable for learning fpga children's shoes, verilog language digital system design, a very good learning materials.)
华为_大规模逻辑设计指导书
- 本文为华为公司内部FPGA开发资料，对提升编程能力有较大帮助。(This paper has a great help for improving the programming ability of HUAWEI's internal FPGA development data.)
verilog黄金参考指南中文版
- 本文是verilog的编程指导书籍，对verilog开发有较大的帮助。(This article is the programming guide book of Verilog, which has great help for the development of Verilog.)
SOPC开发快速入门教程中文版
- 本文为基于QuartusII和NiosII IDE的FPGA/SOPC开发资料，目的是为了尽快掌握FPGA/SOPC的开发流程，投入实践当中。(This paper develops data for FPGA/SOPC based on QuartusII and NiosII IDE. The purpose is to master the development process of FPGA/SOPC as soon as possible and put into practice.
CTE
- YUV訊號轉RGB訊號 RGB訊號轉YUV訊號(YUV to RGB and RGB to YUV)
VGA_to_DVI
- 采用Verilog语言将VGA视频信号转化成DVI视频信号，实现视频信号的转化(Using Verilog language to transform VGA video signal into DVI video signal and realize the transformation of video signal)
ddr3_mig8
- fpga实现ddr数据收发测试，完整的工程，下载解压后，即可正确运行，已多次验证无误(FPGA DDR data receive and receive test, complete engineering, download and unzip, can run correctly, has been verified many times)
axi_ad9361
- AXI_AD9361 的 verilog 驱动工程，包含数据接收，数据发送 AXI总线 ，全部是verliog实现(AXI_AD9361's Verilog drive project, including data reception, data transmission AXI bus, all verliog implementation)
div_3
- 采用Verilog语言对时钟进行3分频，满足系统多时钟频率的要求(3 frequency division of clock in Verilog language to meet the requirement of multi clock frequency of the system)
DS18B20
- 利用FPGA来采集DS18B20数字温度传感器，完成测温采集的功能(The use of FPGA to collect DS18B20 digital temperature sensor to complete the function of temperature measurement and collection)
verilog-stopwatch-master
- verilog stop watch code for end user
Guia_1B
- 0-10-0 counter to 8051 microcontroller in assembly