资源列表
caideng
- 应用VHDL语言编程，实验彩灯控制.本程序经EC3C10E144C8验证无误，请放心使用-Application of VHDL language programming, experimental lantern control procedures by EC3C10E144C8 verify the correct, ease of use
Pattern_Generator
- vip套件中的彩条显示实例vga显示-vip suite color bar display example
vhdl
- NUTAQ 公司的RF 420M 的FMC接口代码 -NUTAQ company' s RF 420M of FMC interface code
random
- 8位伪随机序列发生器。在通信加扰，序列检测中有很强的工程应用-8 pseudo-random sequence generator. In communications scrambling sequence detection has a strong engineering applications
ADDER
- 超前进位加法器。时序好，功能可靠.工程引用已经验证。-Lookahead adder. Timing is good, functional and reliable
VHDL
- VHDL小程序，其中包含了bcd码转换成格雷码、寄存器的简单设计（并入串出移位寄存器、串入串出移位寄存器）以及脉冲发生器的VHDL实现。适合于基础的VHDL入门。-VHDL small program, which includes a bcd code into Gray code, register for a simple design (String into a shift register, the string into the string out of the shift re
8B10B
- 8b/10b编解码实现，很实用。可以借鉴-8b/10b encoding and decoding to achieve, very practical. Can learn
pulse_syn
- 跨异步时钟域单bit处理模式，工程实际应用中，非常有效。-Cross-domain single-bit processing asynchronous clock mode, practical application of engineering, is very effective.
vhdl_01110010
- 一个简易的产生巴克码和巴克码的检测程序，适合于刚刚学习VHDL语言的入门。-A simple code and generate Barker Barker code testing procedures, suitable for just learning VHDL language entry.
i2c_latest.tar
- This module provides a bridge between an I2S serial device (audio ADC, S/PDIF Decoded data) and a parallel device (microcontroller, IP block).
eatfish
- vhdl语言，可以实现大鱼吃小鱼功能的时钟仿真仿真，经过测试可用-vhdl language, can achieve ones devour function clock simulation simulation, tested available
num_clock
- 基于DE0实验板开发的verilog数字钟程序。实现了12/24小时制切换；闹钟；整点报时等功能。-Based on experimental board development DE0 verilog digital clock procedures. To achieve a 12/24 hour switch alarm clock whole point timekeeping function.