资源列表
zhengxianbo
- 正弦波发生器，基于verilog语言编写的，不用用DAC模块，直接输出0和1电频，经过RC滤波后就可得到波形-Sine wave generator, based on verilog language, do not use the DAC module, direct output power frequency 0 and 1, RC-filtered waveform obtained after
acquisition_ad9887a1.3
- FPGA 将ad9887a输出的数据写入FIFO_00中，并计数输入的点频，行频和当前行频。将计数的点频，行频和场频数，以及行场信号输出信号（高电平有效）。 点频计数值为前一行的数据量。行频计数输出是前一场的计数。当前行频计数输出是当前行在这一场的行数。-FPGA will ad9887a output data is written FIFO_00 in and point counting input frequency, line frequency, and current line
clock
- verilog hdl 编写的八位数码管24进制的数字钟，含清零功能-verilog hdl written eight digital tube 24 hex digital clock, with clear function ...
memory
- The pipeline SPIN VHDL code (memory part)
fetch
- The pipeline SPIN VHDL code (fetch part)
TimeClock
- 能够在max3上显示24小时，并且具有定时功能，能够设定闹钟，具有正点报时-Max3 can display 24 hours, and has a timer function, be able to set the alarm, with punctual timekeeping
execute
- The pipeline SPIN VHDL code (execute part)
decode
- The pipeline SPIN VHDL code (decode part)
control
- The Pipeline SPIN model using VHDL
waveform
- The waveform of pulse generator code
pulse_gen
- Pulse generator using VHDL for most of FPGAs
fsk
- 使用quartus13.0 搭建的FSK调制解调仿真系统使用了DDS技术和正交相关解调。-Quartus13.0 built using FSK modulation and demodulation simulation system uses DDS technology and quadrature coherent demodulation.