资源列表
ADC_TCL5510
- 用verilog编写的源代码 可以对此芯片进行相关操作-Written in verilog source code can be related to the operation of this chip
fft4096_8192
- 基于基2的并行4096，8192深度的FFT源代码verilog-Based on radix-2 FFT parallel 4096,8192 depth verilog source code
fft256_512_1024
- 基于基2的并行256，1024深度的FFT源代码verilog-Based on radix-2 FFT parallel 256,1024 depth verilog source code
i2c
- I2C总线协议的verilog 可直接应用 -I2C bus protocol verilog can be applied directly
MPPT_PV_12V_FPGA5
- 基于fpga的mppt（最大功率跟踪）无差拍设计-Fpga-based mppt deadbeat designs. . .
61IC_S2682
- verilog编写 以E2V的CCD 芯片的核心图像采集系统-verilog prepared by E2V CCD chip' s core image acquisition system
DDRSDRAM_
- 基于FPGA 的DDR SDRAM 的重要资料 内附代码-FPGA-based DDR SDRAM code containing important information
miaobiao
- 秒表 8个7段译码器 分钟数——秒数—百分之一秒-Stopwatch 8 7 segment decoder minutes- seconds- hundredths of a second
iic_com
- 用verilog语言实现IIC读写与并通过UART协议在串口PC显示，实现数据收发-IIC using verilog language and literacy with the PC via the serial port UART protocol display, data transceiver
DDS
- 用verilog语言实现，DDS信号发生与嵌入式逻辑分析仪的调用，程序功能完整 -Using verilog language, DDS signal generator with embedded logic analyzer called, the program features a complete
sync-and-asyn_FIFO_verilog
- 同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料-Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references
TLC1556
- 使用10位串行DA芯片TLC5615将数字信号转换为模拟信号，开发板DA芯片VDD=5V,VREF=3.3V 计算公式：Vout=VREF*(N/1024) N为10位二进制码-Use DA chip TLC5615 10 serial digital signal into an analog signal, the board DA chip VDD = 5V, VREF = 3.3V formula: Vout = VREF* (N/1024) N is 10-bit binary