资源列表
YINYUE
- EDA梁祝音乐，但是其中有一个错误，不知道怎么更改-EDA Butterfly music, but there was an error, do not know how to change
serial
- 基于FPGA的串口通讯,能够实现串口助手给fgpa发送16进制的数字，FPGA也能够向串口调试助手发送数据-Based on FPGA, serial port communication can realize serial assistant send fgpa hexadecimal Numbers, the FPGA can also send data to serial debugging assistant
CD1_PHOTO_ABLUM(1920)
- 基于FPGA的1920像素的图片保存显示，图片保存在记忆卡中-FPGA-based 1920 pixel image retention, images stored on the memory card.
CD1_MT9D001_DISPALY_SAVE
- 基于FPGA的CMOS图像传感器（MT9D00）显示并保存图像-FPGA-based CMOS image sensor (MT9D00) and save the image
CD1_OV5620_DISPALY
- 基于FPGA的CMOS图像传感器（OV5620）显示图像-FPGA-based CMOS image sensor (OV5620) image
square-root
- simulink/matlab 实现求实数平方根-using simulink to calulate the sequare root of the integer
CD1_OV7725_DISPLAY_SAVE
- 基于FPGA的CMOS图像传感器（OV7725）显示并保存图像-FPGA-based CMOS image sensor (OV7725) and save the image
CD1_MT9V034C_DISPLAY_SAVE
- 基于FPGA的CMOS图像传感器（MT9V034）显示并保存图像-FPGA-based CMOS image sensor (MT9V034) and save the image
hdl
- 该资料是HDL语言的入门资料，讲解了verilog语法，以及如何综合，布局布线，设置约束等。内容非常详细。-The data is the HDL language introductory information, explain the Verilog syntax, and how integrated placement and routing, set constraints. Very detailed.
wwj
- 基于FPGA的VGA接口时序 分辨率 640*480 源代码-Based on the source code of the FPGA VGA interface timing resolution 640* 480
Viterbi-verilog-codes
- viterbi的无线局域网802.11协议接收端重要的一步。该资料为viterbi的verilog代码，它占用的资源相对比较低，而性能又高。-the viterbi wireless LAN 802.11 receiving end the important step. The viterbi verilog code, it takes up resources is relatively low, and high performance.
FFT_64points
- 64点的 FFT verilog,它是串行计算的，工作频率不到100M，计算速率很高，里面的层次很清晰。-64-point FFT verilog serial computing, the operating frequency of less than 100M, the calculated rate is high, the level inside is very clear.