资源列表
Gps_c_code_nco
- 在GPS接收机本地NCO及CA码产生，生成超前码，即时码和滞后码。-generate NCO and ca coce in gps receiver，generate E_P_L code.
SPI-IP
- 比较经典实用的ip核，对初学者有很大的帮助，语言比较简单。-Classic and practical IP core, a great help for beginners, the language is relatively simple.
FPGA-control-MAX1312
- FPGA控制MAX1312进行数据采集的程序接口程序-FPGA control MAX1312
eda-Lab-report
- 三线八线译码器、数据选择器、数据比较器、二进制编码器、译码器的verilog语言输入方法-Three line eight line decoder, data selector, comparator, the binary encoder and decoder of verilog language input method
32bit_adder
- 三十二位加法器设计，能实现求补、加减法运算并具有溢出标志-Thirty-two adder designed to complement, addition and subtraction operations and overflow flag
lic_Xilinx_ISE_Vivado
- 这是Xilinx ISE 14.X以及vivado、vivado_hls的license，亲测可用-Xilinx ISE 14.x vivado, vivado_hls license, pro-test available
digitPI_control
- 数字式PI比例积分控制器，有关自动控制方面的知识-The digital PI PI controller, the automatic control of knowledge
PIcontrol
- 数字式PI比例积分控制器，有关自动控制方面的知识-The digital PI PI controller, the automatic control of knowledge
PI
- 数字式PI比例积分控制器，有关自动控制方面的知识-The digital PI PI controller, the automatic control of knowledge
FPGA_DDS
- 本程序是基于FPGA的DDS产生任意的波形输出，已经编译完-This procedure is based on FPGA DDS arbitrary waveform output, has already been compiled
Async-FIFO-VHDL
- 异步FIFO VHDL代码实现，包括：async_fifo_show_ahead.vhd， async_fifo_show_ahead_rd_task_logic.vhd，async_fifo_show_ahead_wr_task_logic.vhd， sync_r2w.vhd，sync_ram_std_dc.vhd，sync_w2r.vhd-The asynchronous FIFO VHDL code implementation, including: async_fi
I2C-bus-based-on-FPGA
- 基于FPGA设计I2C总线，使用Verilog语言，ISE环境，含有仿真结果-I2C bus based on FPGA design using Verilog language, ISE environment containing simulation results