资源列表
基于vhdl的抽奖程序
- 用vhdl语言编写的抽奖程序，以led灯的亮灭状态显示抽中哪个灯
fboscl
- 基于FPGA,利用verilog语言实现反馈振荡器，已经仿真无错误-Based FPGA using Verilog language the feedback oscillator simulation error-free
jacobi
- 雅可比算法求解矩阵特征值级特征向量问题，本算法有高速的特点-Jacobi algorithm for solving matrix eigenvalue-level feature vector problem, the algorithm has the characteristics of high-speed
ledvhd
- ISE与VHDL入门程序，使用DCM分频实现LED的控制。-ISE and VHDL entry procedures with DCM divide LED control.
UART0407
- ise平台模拟UART，并与PC机实现收发（+1）-ISE platform simulation UART and transceiver.
dds
- 基于FPGA，利用vhdl语言结合matlab工具实现dds,已经仿真-Based on FPGA, VHDL language with matlab tools to achieve DDS, has simulation
clk_div
- 实现时钟的四分频和16分频，用Verilog语言编写，并经过Quartus仿真-Clock divided by four and divided by 16
CNTRTEST3_7tx_rx_0422
- 在ISE12.4与TMS320F2812的XINTF接口，实现数据收发-In ISE12.4 TMS320F2812 the XINTF, data transceiver
chuankou
- 基于FPGA，利用vhdl语言实现串口通信，程序已仿真-Based on FPGA, VHDL language serial communication, a simulation program
vhdl-_hamming
- 基于FPGA，利用vhdl语言实现hamming编码的一段程序，已经仿真过-Based on FPGA, VHDL language hamming coding a program simulation
digital-clock
- 采用verilog语言将输出频率分频实现数字钟的基本功能：如时间显示，定点报时，整点报时，倒计时等。-Using verilog language to realize the basic function of digital clock by cut the output frequency , such as showing time, designated time,, countdown, etc.
vhdl_miaobiao
- 基于FPGA，VHDL实现秒表功能，利用了分频和计数-FPGA, VHDL-based stopwatch function, the use of divide and count