资源列表
mokekong
- 模可控计数器的设计，顶层文件，仿真文件，等等。-Mold controllable counter design, top-level document, simulation files, and so on.
zhengxian
- verilog的正弦函数信号发生器的设计。可生成不同的正弦函数信号波形。-verilog sine function signal generator design. Can generate a different signal waveform of the sine function.
dianji
- 直流电机综合测控系统的设计、直流电机驱动控制电路顶层设计-The design of the integrated monitoring and control system of the DC motor, DC motor drive control circuit top-level design
shuzizhong
- 数字钟verilog程序，实现了校时、闹钟校正、整点报时功能。-Digital clock verilog program, school, alarm clock correction, the whole point timekeeping function.
counter60
- 利用实验板实现模六十计数，即00—01—02—03—04—…59—00—01…，并在Basys2实验板的AN1~AN0与（LD7~LD0）上显示。-Experimental plate to achieve mode 60 counts, namely 00-01-02-03-04- ... 59-00-01 ... AN1 ~ AN0 Basys2 experiment board with (LD7 ~ LD0).
Quadruple-2-Input-Exclusive-Or-Gates
- quadruple dual input exclusive or gates
Four-Consecutive-Ones-Detector
- its a counter of four ones consecutive
Comparador
- its a comparator of 4bits with ins cascade-its a comparator of 4bits with ins cascade
ffjk
- its a flip flop jk based in quartus II altera
divisor_frecuencia
- its a divider clock. its possible select the frequency based in a master clock
Verilog_prj
- 特权同学书籍《深入浅出玩转FPGA》的源码 -Privileged students books layman Fun FPGA source
spi
- 利用verilog语言 实现spi协议功能-verilog achieve spi protocol functions.