资源列表
偶数分频器源代码（可移植）
- FPGA奇偶分频器 可移植 原工程文件 试验没有问题-The FPGA parity divider, portable the original project file
filter
- 基于VHDL的FIR数字滤波器的设计，可以自己修改参数设置滤波器阶数-FIR digital filter design based on VHDL, can modify the parameters to set the filter order
shfrtled
- 使用状态机思想实现VHDL LED跑马灯功能-Thinking of using the state machine VHDL LED Marquee function
PS2键盘实验－识别0-9和A-F 数码管显示值
- VHDL FPGA驱动键盘工程及源代码 试验已经通过 直接下载使用-VHDL FPGA driven keyboard Engineering and source code test has been used through direct download
Divider
- 除法的fpga实现 开发环境ise 语言vhdl-divider ise vhdl fpga
elevator
- 改程序是电梯的控制程序，verilog语言编写-The reform program is the elevator control procedures, verilog language write
CPLD-digital-clock-design
- 基于CPLD实验板的多功能数字钟设计，运用VHDL编写程序-Multifunction digital clock design based on CPLD experimental board, the use of VHDL programming
Altera-SDRAM_controller-IP-CORE
- ALTRA官方提供的SDRAM的控制内核，VHDL和VERILOG版本都有，希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
ADD
- Verilog编写的Altera单精度加法器源码-Altera single precision adder source Verilog prepared
E4CE40_TV_PAL
- Altera E4CE40 TV PAL制式 源码-Altera E4CE40 TV PAL standard source
HalfFilterMatlab_11
- 半带滤波器的matlab设计 生成fpga所要的数据-halfband matlab
1286400
- VHDL FPGA128*64显示中文撤程序 下载试验均已成功-VHDL FPGA128* 64 display Chinese withdrawal program download trials have been successful