资源列表
9_TheBell
- FPGA，VHDL语言 蜂鸣器 响0.5S~~，时钟分频源程序，适用于所有FPGA芯片-FPGA, VHDL language buzzer 0.5S ~ ~, clock divider source, applicable to all FPGA chip! !
2_KeyLED
- FPGA，VHDL语言 用按键点亮一个灯，适用于所有FPGA芯片，可重新分配引脚-FPGA, VHDL language with the keys lit a lamp, applies to all FPGA chip and can reallocate pin! !
7_DynDigTub
- FPGA，VHDL语言动态显示一位数码管，使用所有FPGA芯片，课重新分配引脚-FPGA, VHDL language dynamically display a digital tube, all FPGA chip, the lesson reallocate pin! !
LCD-Driver-And-Keyboard-char-Asm(www.bargh20.com)
- LCD Driver And Keyboard char Asm(www.bargh20.com)
sv
- stack and events in system verilog
EDA
- VHDL实现一个整点报时的秒表第一个子程序-VHDL achieve a integral point time of the stopwatch 1
tanchishe
- verilog编写的贪吃蛇小游戏，能够在vga上显示，可以通过sp3键盘控制蛇的运动，吃食物-verilog prepared by the Snake game, vga on display by sp3 keyboard to control the movement of the snake to eat the food
a1
- 1 bit MUX 用ISE写的1bit MUX的verilog code 可以在ISE上模拟1bit MUX的运作-1 bit MUX It is a file of verilog code to design a 1 bit MUX. It is design by ISEbit
sdram
- 自己做的一个SDRAM控制器，供大家参考啊！-Own a SDRAM controller for your reference!
sgmii_latest.tar
- This core implements Physical Coding Sublayer of 1000BaseX transmission (IEEE 802.3 Clause36 and 37). This core can also be used for SGMII interface as this interface leverages 1000BaseX PCS. The differences between the 2 protocols are Link-timer and
axi_master_latest.tar
- RobustVerilog generic AXI master stub源码，包括文档说明-RobustVerilog generic AXI master stub
minimips_latest.tar
- minimips MIPS CPU源码，包括文档说明-minimips CPU source code documentation etc