资源列表
Digital_Clock
- 用verilog写的数字时钟代码，亲测可用，可自行编写test bench进行仿真(Written in Verilog digital clock code, pro test available, you can write your own test bench for simulation)
sp6ex15
- SRAM读写测试，每秒进行一次单字节SRAM读写，使用chipscope观察时序波形(SRAM read and write test, a single byte SRAM read and write every second, using chipscope to observe the timing waveform)
9959_1chan
- 对ADI公司的AD9959芯片编程，实现SPI通信(ADI company AD9959 chip programming, SPI communication)
encoder_clk
- 精确实现奇数分频，将FPGA开发板提供的25MHZ时钟分频为1MHZ，内含测试文件(Accurate realization of odd frequency division, the FPGA development board provides 25MHZ clock frequency divided into 1MHZ, containing test files)
Verilog HDL program
- 文件详细讲述了使用XILINX产FPGA在ISE平台开发的方法，介绍了Modelsim，chipscope,textbench等仿真方法，并含大量实例以及源代码(File details on the use of XILINX produced FPGA in the ISE platform development methods, introduced the Modelsim, chipscope, textbench and other simulation methods, and
New folder
- clock div testbench design and frquency division
led4
- 数码管动态显示，显示的字符大概14位，动态扫描时间1ms，还是挺好用的(Digital tube dynamic display)
program
- Built in self test to such that it generates non redundant inputs to tester using the concept of galois based primitive polynomial.
sdram controller
- Introduction Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide hidden precharge time and t
snake
- Gradient Vector Flow (GVF) snake is one kind of active contours - curves that can move within images to find the boundaries of objects. 3D active contours are also known as deformable models. GVF snake begins with calculating the GVF force field over
MP3 VHDL
- MP3 Decoder written in VHDL.
DE1_TOP
- ad转换DE1板子，14位AD，并行AD转换(AD conversion DE1 board, 14 bit AD, parallel AD conversion)