资源列表
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- 基于matlab和QuartusII开发的无线通信FPGA设计,内有(matlab代码,Verilog代码,缩略语表.doc)注释详细,代码数十个,总有一个是你喜欢的!-Matlab and QuartusII based on the development of wireless communications FPGA design, there are (matlab code, Verilog code abbreviations. Doc) Notes detail dozens of
MULT
- 乘法器 verilog CPLD EPM1270 源代码-Multiplier verilog CPLDEPM1270 source code
tetrix_vhdl
- 使用vhdl实现的俄罗斯方块，包含mds图和源代码-Tetris using vhdl implementation, including diagrams and source code mds
ISE_lab19
- 俄罗斯方块VHDL实现，。该设计由下面模块组成：键盘输入模块，游戏控制模块，图像显示模块，文字显示模块，存储单元，复用单元和VGA 控制模块组成。其中图像显示模块和文字显示模块复用VGA 控制模块。游戏控制模块，图像显示模块和文字显示模块通过存储单元交换数据。-Tetris VHDL implementation. The design consists of the following modules: Keyboard input module, the game control modul
control_fsm_rtl.vhd
- ALU 有限状态机 ALU 有限状态机 ALU 有限状态机 ALU 有限状态机 ALU 有限状态机-ALU FSMALU FSMALU FSMALU FSMALU FSMALU FSMALU FSMALU FSM
SPI
- VHDL语言编写的SPI通信接口,可实现与单片机等外部MCU的通信,且只占用较少的引脚线-Written in VHDL SPI communication interface, can be realized with the microcontroller and other external MCU communication, and only takes less pin line
AD9833
- AD9833输出正弦波、三角波及方波，希望对大家有用-AD9833 output sine wave, square wave triangle spread, want to be useful
AD9833
- VHDL语言 状态机实现AD9833信号的产生-VHDL language state machine to achieve AD9833 signal generation
FPGA_Clk
- 基于Cyclone EP1C6240C8 FPGA的时钟产生模块。主要用于为FPGA系统其他模块产生时钟信号。采用verilog编写。 使用计时器的方式产生时钟波形。 提供对于FPGA时钟的偶数分频、奇数分频、始终脉冲宽度等功能。-Based on Cyclone EP1C6240C8 FPGA' s clock generator module. Is mainly used for the FPGA system clock signal generated in other
Electronicorgan
- 利用VHDL编写的电子琴发生器，以简单的演奏电路论文-Electronic organ prepared using VHDL generator to perform a simple circuit Papers
DE2_CCD_PIP
- 实现DE2上的摄像头采集，实现画中画，利用两个摄像头，在VGA上实现两个画面同时出现-DE2 on the camera to achieve the collection, to achieve PIP, using two cameras, the VGA screen to achieve two concurrent
xapp716_release
- 基于FPGA的SATA控制器，可以完成SATA1.0协议-FPGA-based SATA controller, you can complete SATA1.0 agreement