资源列表
fifo
- fifo模块，改模块使用同步fifo设计，里面包含一些设计技巧，读延迟最少(The module of FIFO is modified by using synchronous FIFO, which contains some design skills and the least latency.)
8815397fft
- 基于MATLAB/FPGA的fft的verilog实现。(Verilog implementation of FFT based on MATLAB/FPGA)
dpram
- 在quartus ii平台上，通过代码实现DPRAM，文件夹中包含仿真文件。(generate DPRAM through verilog)
FPGA实现AD8556采集程序设计
- 基于ADS8556的FPGA数据采集程序设计。(The design of FPGA data acquisition program based on ADS8556.)
ARS_SHA_1
- sha-1主控制模块实现了对整个sha-1流程的控制(The SHA-1 main control module realizes the control of the whole SHA-1 process.)
28_ad9226_test
- 此程序完成了的双路数据的采集，通过ad模块将模拟数据转化为12位数字信号，并通过串口发送在pc端的串口助手中显示(This program has completed the acquisition of dual data. Through the ad module, the analog data is converted into 12 bit digital signals and is sent to the serial port assistant at the PC side
usb2.0调试助手
- 基于usb2.0的C++上位机，实测可用，仅供参考(USB2.0 based C++ upper computer, measured available, for reference only.)
VmodCAM_Ref_HD Demo_13
- This project has dependencies in the 'digilent' VHDL library. For your convenience a local copy of these dependencies are included in the remote_sources directory. The VmodCAM_Ref_HD demo project was built around an Atlys+VmodCAM setup. The proj
initial_lib
- Vivado的初始库文件，内含74LS系列IP模块和XUP系列模块(The initial library file of Vivado contains 74LS series IP module and XUP series module.)
binary multiplier
- verilog code for binary multiplier
vhdl
- 用VHDL语言实现CD4527（BCD比例乘法器）仿真(The simulation of CD4527(BCD proportional multiplier))
PC2FPGA_UART_Test
- 基于 fpga 的 uart 设计 波特率 115200(UART design based on FPGA)