- powerelec1 电力电子环流SIMULINK模型 Notice that the Thyristor blocks have an output identified by the letter m. This output returns a Simulink vectorized signal containing the thyristor current (Iak) and voltage (Vak).
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资源列表
dds_ise7.1_su
- 用Verilog语言实现信号发生器，包括AM，FM,PM，ASK,PSK,FSK调制。-using Verilog language signal generator, including AM, FM, PM, ASK, PSK, FSK modulation.
cpldPWM
- verilog HDL 编写的PWM，是初学CPLD者入门Z资源，epm7128stc100-10-verilog HDL prepared by the PWM, is a novice CPLD Getting Started Z resources, epm7128stc100-10
verilogled
- cpld-epm7128stc100-10驱动四位LED结果显示1234-cpld - epm7128stc100-10 drive four LED 1234 results
traffic2
- 用verilog编的小程序,希望对需要的人有所帮助-verilog series with a small procedure, and I hope to the people in need some help
sdram_verilog
- 这是使用VERILOG语言，基于MICRON公司的SDRAM开发的SDRAM接口逻辑-verilog This is the use of language, MICRON-based company's development of the SDRAM SDRAM interface logic
simple_cpu
- 初学cpu结构的很好的verilog代码的示例，适合初学者-novice cpu structure of the good verilog code examples for beginners
DigitalClockVHDL
- 多功能电子时钟的VHDL源代码。使用MAX+PLUS II进行编译。该文档有详细的说明和程序注释。-VHDL source code. Use MAX PLUS II computer. The document is described in detail in the Notes and procedures.
VHDL-status
- VHDL状态机学习笔记,对初学者有很重要的帮助意义-VHDL state machine learning notes for beginners has a very important significance help
Verilogmanual
- VERILOG语言速查手册,与VHDL齐名的另外一硬件描述语言-verilog language manuals, and the other enjoying VHDL hardware descr iption language 1
three-vhdl
- VHDL下实现3分频率波形,完整源代码,学习参考-VHDL under three frequency waveform, complete source code, study reference
ndivider
- VHDL源代码实现任意个分频,值得推荐学习-VHDL source code to achieve arbitrary sub-frequency, it is worth learning recommended
shockware
- VHDL 波形防止抖动程序,学习试验材料-VHDL prevent jitter waveform procedures, the pilot study materials