资源列表
cdr
- 数据时钟恢复，采样8倍率高频时钟进行数据时钟恢复。已通过Modelsim仿真-Data and clock recovery, sampling 8 times the rate of high frequency clock for clock and data recovery. Have been through the Modelsim simulation
UG586-7SeriesDMIUserGuide
- UG586 - Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB )-UG586- Zynq-7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2.3 User Guide ( ver2.3, 18511 KB )
DE2_115_PS2_DEMO
- 完成确定鼠标目前的位置X,Y轴，以及对鼠标三键的检测。-Completion determination mouse current position X, Y-axis, and detection of mouse triple bond.
plus1
- 3位二进制运算器及其数码管扫描显示电路3 binary arithmetic and digital scanning display circuit-3 binary arithmetic and digital scanning display circuit
axi_dispctrl
- zynq AXI display controller source for zybo
zynq-xdma
- zynq xdma source code
microzed-axi-dma
- microzed (zynq) axi dma source vhdl
microzed_tft
- TFT on microzed vhdl source code
vga
- 一个简单的VGA小应用，实现功能是一个红色小方块，可以在屏幕上沿任意方向移动，如果碰到屏幕边缘，可以反弹回去。-A very easy VGA test case
multiplier
- Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support
proje-vhdl
- ASYMMETRIC LARGE SIZE MULTIPLIERS WITH OPTIMISED FPGA RESOURCE UTILISATION
uart_verilog
- 232串口Verilog语言实现，可供新手参考编写，不太完善，需做补充。-Uart 232 Verilog