资源列表
i2c_master_slave_core.tar
- I2C verilog HDL code including test environment
vga
- vga实现汉字显示，只有。v和ucf文件 基于sprtan3e板-vga word print
component_timer_counter
- Quartus环境下基于VHDL元件例化的数字钟程序-Zhong Chengxu digital VHDL component instantiation based on Quartus environment
jiaotongdeng
- Quartus2环境下基于VHDL状态机的交通灯程序-VHDL state machine traffic lights based on Quartus2 environment
v2
- rs422串口指令控制以及AD7824芯片的数据采集-rs422 serial control timing
Example8
- 一个基于FPGA的4位流水乘法器的小程序，设置了时钟输入，数据输入，并输出结果。-One of four water-based FPGA multiplier applet, set the clock input, data input and output.
Example7
- 一个基于FPGA的步长可变加减计数器的小程序，时钟输入，增、减控制信号，转换结果。-An FPGA-based variable step-down counter applet, a clock input, add, subtract control signal, the conversion result.
Example5
- 一款基于FPGA的数控分频器的小程序，定义时钟信号，输入控制的数据，分频输出，波形观测输出。-An FPGA-based applet NC divider, the definition of the clock signal, the input control data, frequency output, the output waveform observation.
Example4
- 一款基于FPGA的数码显示译码器的小程序，定义动态扫描时钟信号，定义四位输入信号，检测时钟上升沿，计数器dount累加。-An FPGA-based digital display decoder small program, define dynamic scan clock signal, the definition of four input signals, detects the rising edge of the clock, the counter dount accumula
Example3
- 一个基于FPGA的计数器的小程序，定义时钟、异步复位、同步使能信号，计算结果。-An FPGA-based counter applet, define the clock, asynchronous reset, synchronous enable signal, the calculation results.
Example2
- 一个基于FPGA的格雷码转换器的小程序，输入8位格雷码并转换结果。-A gray code converter FPGA-based small program, input 8-bit Gray code and conversion results.
Example9
- 一个基于FPGA的四位全加器的小程序，输入两个二进制数并计算结果。-An FPGA-based four full adder applet, enter two binary numbers and calculations.