资源列表
18_uart
- 通过FPGA建立模块的串行的Verilog实现-Realized through the establishment of the module s serial verilog on FPGA
control
- implementation of a control system analysis.
STM32_Time
- 这个实验是STM32定时器中断实验。控制LED灯亮或者灭-This experiment STM32 timer interrupt experiments. Control the LED lights off or
STM32_-USART
- 这个实验是STM32串口实验，中断接收数据。-This experiment is the experiment STM32 serial interrupt receive data.
STM32_EXIT
- 这个实验是STM32外部中断实验。控制LED灯亮灭-This experiment STM32 external interrupt experiment. Control LED lights off
2014
- 2014年飞思卡尔智能车比赛电磁组的主板设计，-2014 Freescale smart car group game electromagnetic motherboard design,
ddr_controller
- 完整的DDR控制器设计，包含代码、仿真环境、FPGA综合网表等-full DDR controller ip,include rtl code,simulation environment and testbench, fpga synthesis netlist,etc.
Cascaded_EDAFs
- optical cascaded EDAF amplifiers design