资源列表
freq_divider7
- 本程序为七分频数字电路的实现，采用VHDL语言编程，采用常见的奇数次分频方法实现，进仿真证实可用。其他奇数次可以直接修改程序中相关参数值即可直接移植引用-This procedure is the seventh-frequency digital circuits implemented using VHDL language programming, using a common method to achieve the odd division into simulation confi
xiaoche
- 电机驱动程序，基于L298N的电机驱动Python编程-The motor driver, driven by L298N, drives the Python programming
IIC24C02
- 24C02程序，写一个字节，读一个字节，任意地址写入一个字节，任意地址读出一个字节-IICprogram,write one byte,read one byte,any address write one byte,any address read one byte
TB6560C
- TB6560驱动 用来驱动TB6560 51单片机编写-TB6560 drive
E4_1_fir1
- 基于ip核的fir滤波器设计，调用了ip核，并实例化，对初学者很有用。-Based on the ip kernel fir filter design, call the ip kernel, and instantiation, very useful for beginners.
8key
- 8个按键控制二极管不同的亮灭显示，蜂鸣器不同的声调-Eight key control diode destroy the light of different display, buzzer different tones
memTB
- it is a testbench describing the function of a memory
BodePlots
- 利用MATLAB实现一种单相逆变器的控制系统波特图分析- U5229 u758MATCC u5B9E u73B0 u4E00 u79CD u5355 u76F8 u9006 u53D8 u5668 u7684 u63A7 u5236 u7CFB u7EDF u6CE2 u7279 u56FE u5206 u6790
EF1
- Pspice Emitter Follow
KEY44
- 矩阵键盘，行列扫描。封装成固定函数，使用超核库(Matrix keyboard, row and column scanning)
常用加法器设计
- 采用Verilog设计的几种常用加法器。(several adder designed by Verilog)
计数器
- 简单的硬件描述语言verilog语言描述的128进制计数器。(Simple hardware descr iption Language Verilog language described 128 binary counter.)